1. Field of the Invention
The present invention relates generally to field of detection of fault of a computer system, and in particular to a control device that prevents hardware strapping fault of integrated circuit (IC) device of the computer.
2. The Related Art
With the continuous improvement of computer capacity, hardware architecture of the computer becomes increasingly complicated. In response to such a trend, computer designers and manufactures are facing challenge of developing computers of high performance and high quality under the constraints of limited footprint and limited number of pins. Thus, most of the integrated circuit devices incorporated in the computers are of a multiplexing configuration. In other words, a single pin of the integrated circuit may perform a variety of operations.
FIG. 1 of the attached drawings shows a simplified functional circuit block diagram of an existing computer system, which comprises a central processing unit 10 connected to a north bridge 11 via a host bus. The north bridge 11 is also referred to as “Host Bridge”. A main memory 12 is coupled to the north bridge 11 via a memory bus. An accelerated graphic port (AGP) display device 13 is coupled to the north bridge 11 via an AGP bus.
The north bridge 11 is coupled to a south bridge 14 via a high speed bus, such as a V-Link bus that has a data transmission rate as high as 266 Mb per second. The south bridge 14 is connected to a plurality of peripheral component interconnect (PCI) slots 15, which allows for connection with PCI devices (not shown) of different functions, via a PCI bus. The south bridge 14 is also connectable with an IDE interface based external device 16, such as an optic disk drive, via an IDE bus.
In such a computer system, multi-frequency, multiplexing clock generator 17 is incorporated to provide a variety of clocking signals to the previously-mentioned components and devices as working frequencies thereof.
One of the multiplexing pins of the IC devices incorporated in a computer system is the so-called “hardware strapping pin”, which is locked in a rising edge or falling edge of a system reset signal in order to determine initial condition of hardware and which returns to original pin function after the reset cycle. Since the hard strapping pin is of a multiplexing design, mis-determination often occurs when an external device is connected to the computer.
Taking the computer system of FIG. 1 as an example, the clock generator 17, such as model number ICS950902 which is a 8375 clock generator, has three hardware strapping pins, namely pin numbers 6 (Model_SEL), 7 (CPU_SEL), and 10 (FS1). The FS1 pin is coupled to the central processing unit 10 and the south bridge 14, respectively. In powering on, the FS1 pin of the clock generator 17 straps a signal from the central processing unit 10 in order to provide correct working frequency f1, such as 100/133 MHz, via a clock signal output pin CPU_CLK, to the central processing unit 10. Thereafter, the FS1 pin of the clock generator 17 is converted into an output pin that supplies a working frequency f2, such as 33 MHz, to the PCI bus of the south bridge 14.
Taking the south bridge 14, such as 8375 south bridge chip, as another example, the south bridge 14 has a hardware strapping pin SDA1 connected to an output pin Y3 of the central processing unit and a signal pin SDA1′ of the external device 16. In powering on, the hardware strapping pin SDA1 of the south bridge 14 performs hardware strapping over the signal pin Y3 of the central processing unit 10 and, thereafter, the hardware strapping pin SDA1 of the south bridge 14 is converted into an output pin, serving as a signal pin between the external device 16 and the south bridge 14.
Normally, when the hardware strapping pin SDA1 of the south bridge 14 performs hardware strapping over the central processing unit 10, the south bridge 14 receives a low-level signal generated by the central processing unit 10. However, in case the signal pin SDA1′ of the external device 16 comprises an internal pull-high resistor, when the hardware strapping pin SDA1 of the south bridge 14 is strapping the central processing unit 10, the external device 16 is in an initialization process, which causes an incorrect result of the hardware strapping performed by the SDA1 pin of the south bridge 14. Further, in case of a mismatch in timing occurs between the external device 16 and the south bridge 14 and the central processing unit 10, incorrect result of the hardware strapping occurs similarly. Besides the computer system discussed above, a variety of control device and equipment that operates on the basis of digital signals and requires connection with external devices encounter such hardware strapping problems.